1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor device. More particularly, the present invention generally relates to a method for manufacturing a semiconductor device having a copper diffusion-prevention layer.
A claim of priority is made to Korean Patent Application No. 2004-3766, filed on Jan. 19, 2004, the contents of which are herein incorporated by reference.
2. Description of the Related Arts
Aluminum wiring has been conventionally used in semiconductor devices because of its low contact resistance and ease of use. As the semiconductor device has gotten highly integrated, the width of wires have gotten narrower and the length longer. As a result, wire resistance and parasite capacitance have increased. To overcome these problems, other metals with good electromigration have been used. For example, copper with its low specific resistance of about 1.6 μΩ·cm and good electromigration has been used. Currently copper wiring is widely used in semiconductor devices.
However, during or after the formation of the copper wires on a semiconductor substrate, copper atoms tend to diffuse into the semiconductor substrate, which deteriorate characteristics of the semiconductor device. To prevent copper diffusion, a diffusion-prevention layer is formed on the underside of the semiconductor substrate prior to the formation of the copper wiring.
FIGS. 1A to 1E are cross sectional views illustrating a conventional method for forming a copper wiring in a semiconductor device.
Referring to FIG. 1A, an isolation layer 12 is formed in a silicon substrate 10. Isolation layer 12 divides substrate 10 into an active region and a field region. A gate electrode 16 with a gate insulation layer 14 is formed in the active region.
Referring to FIG. 1B, low concentration of first impurities are implanted into substrate 10 using gate electrode 16 and gate insulation layer 14 as an ion implanting mask to form lightly doped source/drain regions 20 on substrate 10. As a result, a channel region 22 is formed under gate electrode 16 and gate insulation layer 14 between lightly doped source/drain regions 20.
Referring to FIG. 1C, a gate spacer layer 24 is formed on substrate 10 and gate electrode 16. Also, a copper diffusion-prevention layer 27 is formed on the underside of substrate 10. Copper diffusion-prevention layer 27 prevents copper atoms from diffusing into substrate 10 in a subsequent copper wiring formation step. Gate spacer layer 24 is formed by a low pressure chemical vapor deposition (LPCVD) process at a high temperature. However, the high temperature causes the impurities in source/drain regions 20 to diffuse further into substrate 10 causing source/drain regions 22a to expand, thus narrowing channel region 22a. 
Referring to FIG. 1D, gate spacer layer 24 is etched-back to form a gate spacer 24a on sidewalls of gate electrode 16. High concentration of second impurities are implanted into substrate 10 using gate electrode 16 and gate spacer 24a as an ion implanting mask to form heavily doped source/drain regions 26. Silicide layers 28a, 28b are formed on gate electrode 16 and heavily doped source/drain regions 26, respectively.
Referring to FIG. 1E, an insulating interlayer (not shown) is formed on silicide layers 28a, 28b, gate spacer 24a, and isolation layer 12. The insulating interlayer is partially etched to expose gate electrode 16 and silicide layers 28a, 28b to form an insulating interlayer pattern 30 having a plurality of contact holes. A copper layer (not shown) is formed on insulating interlayer pattern 30 to fill the plurality of contact holes. The copper layer is patterned to form a copper wiring 32.
However, as described with reference to FIG. 1C, the impurities in lightly doped source/drain regions 20 diffuse into substrate 10 due to the high temperature used during the formation of gate spacer layer 24, which reduces the length of channel region 22a. This phenomenon causes a punch-through, reducing the threshold voltage. The phenomenon is referred to as a short channel effect.